The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Aug. 07, 2018
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

François Tailliet, Fuveau, FR;

Marc Battista, Allauch, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 27/11526 (2017.01); G11C 16/06 (2006.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); G11C 5/02 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11526 (2013.01); G11C 5/025 (2013.01); G11C 16/0433 (2013.01); G11C 16/06 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01);
Abstract

A memory device includes a memory plane including a succession of neighboring semiconductor recesses of a first type of conductivity, wherein each semiconductor recess houses a plurality of memory words including a plurality of memory cells, wherein each memory cell includes a state transistor having a floating gate and a control gate. The memory device further includes a plurality of control gate selection transistors respectively allocated to each memory word of the plurality of memory words, wherein each control gate selection transistor is coupled to the control gates of the state transistors of the memory word to which the control gate selection transistor is allocated, wherein each control gate selection transistor is situated in and on a neighbor semiconductor recess of the semiconductor recess housing the memory word to which the control gate selection transistor is allocated.


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