The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2020
Filed:
Apr. 13, 2018
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Eunjung Kim, Daegu, KR;
Daeik Kim, Hwaseong-si, KR;
Bong-Soo Kim, Yongin-si, KR;
Jemin Park, Suwon-si, KR;
Semyeong Jang, Gunpo-si, KR;
Yoosang Hwang, Suwon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.