The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Mar. 21, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jin-Ping Han, Yorktown Heights, NY (US);

Yulong Li, Hartsdale, NY (US);

Dennis M. Newns, Yorktown Heights, NY (US);

Paul M. Solomon, Yorktown Heights, NY (US);

Xiao Sun, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/1159 (2017.01); H01L 21/28 (2006.01); H01L 27/11507 (2017.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 27/1159 (2013.01); H01L 27/11507 (2013.01); H01L 29/0649 (2013.01); H01L 29/40111 (2019.08); H01L 29/4966 (2013.01); H01L 29/516 (2013.01);
Abstract

A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.


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