The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Sep. 11, 2018
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Masato Oda, Yokohama, JP;

Shinichi Yasuda, Setagaya, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); G11C 8/00 (2006.01); G11C 11/40 (2006.01); G11C 11/417 (2006.01); G11C 8/16 (2006.01); H01L 21/8244 (2006.01); H01L 27/11 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/419 (2013.01); G11C 8/16 (2013.01); H01L 27/11 (2013.01);
Abstract

A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.


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