The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Dec. 14, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Yun Du, San Diego, CA (US);

Liang Han, San Diego, CA (US);

Lin Chen, San Diego, CA (US);

Chihong Zhang, San Diego, CA (US);

Hongjiang Shang, San Diego, CA (US);

Jing Wu, San Diego, CA (US);

Zilin Ying, San Diego, CA (US);

Chun Yu, Rancho Santa Fe, CA (US);

Guofang Jiao, San Diego, CA (US);

Andrew Gruber, Arlington, MA (US);

Eric Demers, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06T 1/20 (2006.01); G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30123 (2013.01); G06F 8/441 (2013.01); G06F 9/3012 (2013.01); G06F 9/30141 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06T 1/20 (2013.01);
Abstract

Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.


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