The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Feb. 27, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventor:

Hiromitsu Komai, Kamakura Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01); G11C 7/08 (2006.01); H01L 27/11573 (2017.01); H01L 27/1157 (2017.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0679 (2013.01); G11C 7/08 (2013.01); G11C 7/1006 (2013.01); G11C 7/18 (2013.01); G11C 16/0466 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 2207/002 (2013.01);
Abstract

A semiconductor storage device includes a hookup circuit including first and second circuits connected respectively to first and second bit lines, a first circuit group including a first sense amplifier circuit connected to the first circuit and a first data register connected to the first sense amplifier circuit, a second circuit group including a second sense amplifier circuit connected to the second circuit and a second data register connected to the second sense amplifier circuit, and a memory cell array that is above the hookup circuit and the first and second circuit groups and includes a first memory cell connected to the first bit line and a second memory cell connected to the second bit line. The first circuit group, the hookup circuit, and the second circuit group are arranged in sequence along a first direction that is parallel to a surface of the semiconductor substrate.


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