The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Sep. 07, 2018
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Tadayoshi Miyamoto, Sakai, JP;

Yoshinobu Nakamura, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); G02F 1/136 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13454 (2013.01); G02F 1/1368 (2013.01); G02F 1/133345 (2013.01); G02F 1/134363 (2013.01); G02F 1/136209 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); G09G 3/3648 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 29/41733 (2013.01); H01L 29/7869 (2013.01); G02F 2001/13606 (2013.01); G02F 2001/13685 (2013.01); G02F 2001/134372 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0297 (2013.01);
Abstract

In a demultiplexer circuit, each unit circuit includes at least n TFTsand n branch lines connected with one video signal line. Each TFTincludes an oxide semiconductor layer, an upper gate electrodeprovided on the oxide semiconductor layer with a gate insulating layerinterposed therebetween, and a first electrodeand a second electrode. The demultiplexer circuit further includes a first interlayer insulating layercovering the oxide semiconductor layer and the upper gate electrode and a second interlayer insulating layerprovided on the first interlayer insulating layer. The first electrodeis provided between the first interlayer insulating layerand the second interlayer insulating layerand is in contact with the oxide semiconductor layer inside a first contact hole CHformed in the first interlayer insulating layer. The second electrodeis provided on the second interlayer insulating layerand is in contact with the oxide semiconductor layer inside a second contact hole CHformed in the first and second interlayer insulating layers.


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