The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Aug. 17, 2018
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Hans Weber, Bayerisch Gmain, DE;

Franz Hirler, Isen, DE;

Maximilian Treiber, Munich, DE;

Daniel Tutuc, St. Niklas an der Drau, DE;

Andreas Voerckel, Finkenstein, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/15 (2006.01); H01L 29/66 (2006.01); H01L 21/225 (2006.01); H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0696 (2013.01); H01L 21/2253 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 29/1033 (2013.01); H01L 29/157 (2013.01); H01L 29/158 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01);
Abstract

A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.


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