Array substrate and method of manufacturing the same

Abstract

The present disclosure provides an array substrate and a method of manufacturing the same. The array substrate includes a substrate, a buffer layer, an active layer, a gate insulating layer with a second via hole, a gate, an interlayer insulating layer with a first via hole, a source electrode contacting the active layer through the first and second via holes, a planarization layer with a third via hole, a common electrode with a fourth via hole and a passivation layer sequentially disposed on the substrate, and a pixel electrode disposed on the passivation layer contacts the active layer through a fifth via hole passing through the fourth and third via holes, the interlayer insulating layer, and the gate insulating layer. According to present disclosure, static electricity generated in manufacturing is effectively prevented from being transferred to the active layer to cause Electro-Static discharge, which further improves the product quality.