The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Nov. 07, 2018
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Ki Jun Sung, Cheongju-si, KR;

Ki Bum Kim, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/528 (2013.01); H01L 24/24 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/244 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73267 (2013.01); H01L 2225/06513 (2013.01);
Abstract

A chip stack package includes first and second semiconductor chips. A first redistribution line structure is disposed on a front surface of the first semiconductor chip, and the first redistribution line structure extends onto a side surface of the first semiconductor chip. A second redistribution line structure is disposed on the front surface of the first semiconductor chip, and the second redistribution line structure extends onto the side surface of the first semiconductor chip. A third redistribution line structure is disposed on a front surface of the second semiconductor chip, and the third redistribution line structure extends onto a side surface of the second semiconductor chip to be electrically connected to the second redistribution line structure.


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