The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Dec. 17, 2018
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Yong Il Jung, Gyeonggi-do, KR;

Dae Seok Shin, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G06F 11/10 (2006.01); G11C 29/50 (2006.01); G11C 16/10 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3422 (2013.01); G06F 11/1072 (2013.01); G06F 12/0246 (2013.01); G11C 16/102 (2013.01); G11C 16/349 (2013.01); G11C 29/50004 (2013.01);
Abstract

A memory system includes a storage medium including a memory region group having a plurality of memory regions; a memory configured to store a plurality of region read counts respectively corresponding to the plurality of memory regions and a group read count corresponding to the memory region group; a count management circuit configured to, when a first memory region among the plurality of memory regions is read-accessed, based on a first region read count corresponding to the first memory region among the plurality of region read counts, increase the group read count and reduce remaining region read counts other than the first region read count among the plurality of region read counts; and a reliability management circuit configured to perform a reliability management operation for the memory region group, based on the group read count.


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