The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Feb. 26, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventor:

Rieko Funatsuki, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0035 (2013.01); G06F 3/0619 (2013.01); G06F 3/0638 (2013.01); G06F 3/0679 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0069 (2013.01);
Abstract

A semiconductor memory device includes a memory cell array, a first data latch that retains a write unit of data to be written to the memory cell array, a first address latch that retains a write address indicating a write target destination for the write unit of data in the first data latch, a second data latch that retains fail data that is a write unit of data that has failed to be written to the memory cell array, and a second address latch that retains a fail address indicating a write target destination for the fail data. A controller is configured to output the fail address from the second address latch in response to a first output command requesting output of the fail address and to output the fail data from the second data latch in response to a second output command requesting an output of the fail data.


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