The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Feb. 14, 2018
Applicant:

Longitude Semiconductor S.a.r.l., Luxembourg, LU;

Inventor:

Hideyuki Yoko, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/12 (2006.01); G11C 5/04 (2006.01); G11C 11/408 (2006.01); G11C 5/06 (2006.01); G11C 11/4072 (2006.01);
U.S. Cl.
CPC ...
G11C 8/12 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 11/408 (2013.01); G11C 11/4072 (2013.01);
Abstract

A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.


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