The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2020
Filed:
Mar. 20, 2019
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventor:
Chulho Choi, Seoul, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/038 (2013.01); G09G 5/00 (2006.01); G09G 3/36 (2006.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3688 (2013.01); G09G 3/2092 (2013.01); G09G 3/3648 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/0291 (2013.01); G09G 2330/021 (2013.01); G09G 2330/026 (2013.01); G09G 2330/027 (2013.01); G09G 2330/08 (2013.01); G09G 2370/08 (2013.01);
Abstract
A source driver circuit includes a receiver, a plurality of amplifying buffers, and a control logic circuit. The receiver receives a data signal and a control signal through an input terminal. Each of the amplifying buffers outputs a driving signal generated based on the image data signal through an output terminal. The control logic circuit controls the receiver and the plurality of amplifying buffers based on the control signal. When a power-down signal is provided to the receiver, the control logic circuit is to turn off at least one of the receiver and the plurality of amplifying buffers.