The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Jun. 27, 2018
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Yutaka Mitsuzawa, Tokyo, JP;

Takayuki Nakao, Tokyo, JP;

Yutaka Ozawa, Tokyo, JP;

Masaya Tamaki, Tokyo, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G09G 5/39 (2006.01); H04N 5/3745 (2011.01); G11C 11/16 (2006.01); G11C 11/14 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3614 (2013.01); G09G 3/3655 (2013.01); G09G 3/3677 (2013.01); G09G 3/3688 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G11C 11/14 (2013.01); G11C 11/16 (2013.01);
Abstract

A display device includes: a plurality of sub-pixels each including a memory block; a clock signal output circuit configured to output a plurality of clock signals having different frequencies; a selection circuit configured to select one of the clock signals as a selected clock signal; a plurality of memory selection line groups provided for respective rows; a memory selection circuit configured to output a memory selection signal concurrently to the memory selection line groups in synchronization with the selected clock signal, the memory selection signal being a signal for selecting one from a plurality of memories in each of the memory blocks; a common electrode to which a common potential common to the sub-pixels is supplied; and a common-electrode driving circuit configured to switch the common potential in synchronization with the reference clock signal and output the switched common potential.


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