The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Nov. 10, 2016
Applicants:

Engin Ipek, Rochester, NY (US);

Ben Feinberg, Rochester, NY (US);

Shibo Wang, Rochester, NY (US);

Mahdi N. Bojnordi, Rochester, NY (US);

Ravi Patel, Victor, NY (US);

Eby G. Friedman, Rochester, NY (US);

Inventors:

Engin Ipek, Rochester, NY (US);

Ben Feinberg, Rochester, NY (US);

Shibo Wang, Rochester, NY (US);

Mahdi N. Bojnordi, Rochester, NY (US);

Ravi Patel, Victor, NY (US);

Eby G. Friedman, Rochester, NY (US);

Assignee:

University of Rochester, Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 10/00 (2019.01); G06F 7/38 (2006.01); H01L 39/22 (2006.01); G06F 9/30 (2018.01); G11C 11/16 (2006.01); G11C 11/44 (2006.01); G11C 19/32 (2006.01); H03K 19/195 (2006.01); H01L 27/18 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
G06N 10/00 (2019.01); G06F 7/381 (2013.01); G06F 9/3004 (2013.01); G06F 9/3016 (2013.01); G06F 9/30105 (2013.01); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/44 (2013.01); G11C 19/32 (2013.01); H01L 39/223 (2013.01); H03K 19/195 (2013.01); H01L 27/18 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01);
Abstract

An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.


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