The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Apr. 03, 2017
Applicant:

Western Digital Technologies, Inc., Irvine, CA (US);

Inventors:

Krishanth Skandakumaran, Los Gatos, CA (US);

Arun Kumar Medapati, Andhra Pradesh, IN;

Sri Rama Namala, San Jose, CA (US);

Ashwin Narasimha, Sunnyvale, CA (US);

Ajith Kumar B, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 1/32 (2019.01); G06F 3/06 (2006.01); G06F 11/34 (2006.01); G06F 13/42 (2006.01); G06F 1/3234 (2019.01); G06F 1/3225 (2019.01); G06F 1/329 (2019.01);
U.S. Cl.
CPC ...
G06F 11/3037 (2013.01); G06F 1/329 (2013.01); G06F 1/3225 (2013.01); G06F 1/3253 (2013.01); G06F 1/3268 (2013.01); G06F 3/0625 (2013.01); G06F 11/3041 (2013.01); G06F 11/3062 (2013.01); G06F 11/3495 (2013.01); G06F 13/4282 (2013.01);
Abstract

Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.


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