The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2020
Filed:
Nov. 15, 2017
Qualcomm Incorporated, San Diego, CA (US);
Shivam Priyadarshi, Morrisville, NC (US);
Anil Krishna, Lakeway, TX (US);
Raguram Damodaran, La Jolla, CA (US);
Jeffrey Todd Bridges, Raleigh, NC (US);
Ryan Wells, Raleigh, NC (US);
Norman Gargash, Raleigh, NC (US);
Rodney Wayne Smith, Raleigh, NC (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.