The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Jun. 23, 2017
Applicant:

Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, CN;

Inventor:

Zhichao Zhou, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1368 (2006.01); G02F 1/1362 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1368 (2013.01); G02F 1/1343 (2013.01); G02F 1/1362 (2013.01); G02F 1/13439 (2013.01); G02F 1/134309 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); G02F 2001/134345 (2013.01); G02F 2001/136295 (2013.01); G02F 2201/12 (2013.01); G02F 2201/122 (2013.01); G02F 2201/123 (2013.01); G02F 2201/40 (2013.01);
Abstract

The present disclosure relates to an array substrate, a manufacturing method thereof, and a display panel. Each of the pixel areas correspondingly connects with a data line and a scanning line. In each of the pixel areas, a source of a first TFT and a gate of a second TFT are on the same layer. A gate of the first TFT, a source and a drain of the second TFT, and the scanning line are on the same layer. As such, the present disclosure may avoid the color shift of the vertical alignment (VA) display and may improve the pixel aperture rate.


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