The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

May. 18, 2017
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Shusaku Hayashi, Tokyo, JP;

Kentaro Enoki, Tokyo, JP;

Koichi Akiyama, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/516 (2013.01); H04B 10/556 (2013.01); H04J 14/06 (2006.01); H04B 10/50 (2013.01); G02F 1/025 (2006.01); G02F 1/015 (2006.01);
U.S. Cl.
CPC ...
H04B 10/5161 (2013.01); H04B 10/5053 (2013.01); H04B 10/5057 (2013.01); H04B 10/5561 (2013.01); H04J 14/06 (2013.01); G02F 1/015 (2013.01); G02F 1/025 (2013.01);
Abstract

A timing adjuster shifts a timing between a first data-stream group and a second data-stream group in accordance with a timing setting. A data generator in first test mode generates a first test-data stream repeating 2N-bit marks and 2N-bit spaces as each of a first data stream and a third data stream, and generates a second test-data stream that is N-bit shifted from the first test-data stream, where N denotes a natural number. A first phase-difference setting and a second phase-difference setting are rendered zero. The timing adjuster adjusts the timing setting so as to maximize a detected value from a peak detection circuit.


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