Reducing glitches that occur when multiplexing of asynchronous clocks using flip-flops and logic gates

Abstract

In one embodiment, a method includes receiving an output of a first combinational logic at an enable terminal of a first flip-flop. The first combinational logic inputs include a disable first clock signal from a clock switchover circuit and a disable second clock signal from the clock switchover circuit. A set terminal of the first flip-flop receives an output of a logic gate, and the logic gate receives a select signal and a first clock signal. An input terminal of the first flip-flop receives, an output of a second flip-flop. A reset terminal of the first flip-flop receives an output of a second combinational logic. The second combinational logic inputs include a first clock stopped signal, a power-on-reset signal, and the select signal, the first clock stopped signal indicating a stop in the first clock signal. An output terminal of the first flip-flop outputs a modified select signal.