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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10546952 B1

PDFFull Text
Date of Patent:
Jan. 28, 2020

Filed:

Oct. 16, 2018

Semiconductor device and manufacturing method thereof

Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventor:

Tetsuji Togami, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Tokyo, JP;

Attorney:

Shapiro, Gabor and Rosenberger, PLLC

Primary Examiner:

Stephen M Bradley

Assistant Examiner:

Wasiul Haider

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/02 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01); H01L 21/8234 (2006.01); H01L 21/78 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/30604 (2013.01); H01L 21/76895 (2013.01); H01L 21/78 (2013.01); H01L 21/823475 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 29/0882 (2013.01); H01L 29/41741 (2013.01); H01L 29/66712 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 29/4236 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01);
Abstract

The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

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