The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Oct. 30, 2017
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Shi Shu, Beijing, CN;

Chuanxiang Xu, Beijing, CN;

Teng Luo, Beijing, CN;

Feng Gu, Beijing, CN;

Bin Zhang, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1362 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); G02F 1/1368 (2006.01); H01L 27/32 (2006.01); G02F 1/1343 (2006.01); H01L 21/02 (2006.01); H01L 21/30 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1288 (2013.01); G02F 1/1362 (2013.01); G02F 1/1368 (2013.01); G02F 1/136227 (2013.01); H01L 27/1262 (2013.01); H01L 29/417 (2013.01); H01L 29/42384 (2013.01); H01L 29/66757 (2013.01); H01L 29/78633 (2013.01); H01L 29/78675 (2013.01); G02F 1/134363 (2013.01); G02F 1/136209 (2013.01); G02F 2001/13685 (2013.01); G02F 2001/136231 (2013.01); G02F 2001/136236 (2013.01); G02F 2202/104 (2013.01); H01L 21/02592 (2013.01); H01L 21/02675 (2013.01); H01L 21/3003 (2013.01); H01L 27/3241 (2013.01); H01L 27/3244 (2013.01); H01L 29/7869 (2013.01);
Abstract

A method for fabricating a thin film transistor includes providing a substrate (); forming a semiconductor layer () over the substrate (); forming a source-drain metal layer () over the semiconductor layer (); applying one patterning process to the semiconductor layer () and the source-drain metal layer () to form an active layer (), a source electrode (), and a drain electrode (); forming a gate insulating layer () and an interlayer insulating layer () that cover the active layer (), the source electrode (), and the drain electrode (); applying a patterning process to the interlayer insulating layer () to form a first window () in the interlayer insulating layer () to expose a portion of the gate insulating layer (); and forming a gate electrode () in the first window (). An orthogonal projection of the gate electrode () on the substrate () is in an orthogonal projection of the active layer () on the substrate ().


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