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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10546781 B1

PDFFull Text
Date of Patent:
Jan. 28, 2020

Filed:

Aug. 23, 2017

Display device

Applicant:

Lg Display Co., Ltd, Seoul, KR;

Inventors:

Sun-Hyun Choi, Gyeongsangbuk-do, KR;

Ki-Taeg Shin, Daegu, KR;

Tae-Yun Roh, Gyeongsangbuk-do, KR;

Assignee:

LG Display Co., Ltd., Seoul, KR;

Attorney:

Seed Intellectual Property Law Group LLP

Primary Examiner:

Cuong B Nguyen

Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 21/78 (2006.01); H01L 27/12 (2006.01); H01L 21/66 (2006.01); G02F 1/1362 (2006.01); H01L 21/77 (2017.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); G02F 1/136204 (2013.01); H01L 22/32 (2013.01); H01L 27/1244 (2013.01); H01L 27/1259 (2013.01); G02F 2001/136254 (2013.01); H01L 2021/775 (2013.01);
Abstract

Disclosed is a display device that includes an array substrate that includes a display region and a first non-display region, and includes a signal line connected to a pixel in the display region; a first signal transfer line that is at the first non-display region and transfers a test signal, and a second signal transfer line that transfers a test enable signal; a connection pattern connected to the first signal transfer line; a test transistor that is connected between the signal line and the connection pattern, and is connected to the second signal transfer line; and an electrostatic induction element that includes a dummy device in the form of either a dummy pattern and/or a dummy test transistor, the dummy pattern including a dummy connection pattern connected to the first signal transfer line, the dummy test transistor connected to the second signal transfer line.

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