The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Nov. 19, 2018
Applicants:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Postech Academy-industry Foundation, Pohang-si, KR;

Inventors:

Jaeho Lee, Seoul, KR;

Jaeyoon Sim, Pohang-si, KR;

Kyeongjun Lee, Pohang-si, KR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 11/54 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/54 (2013.01);
Abstract

A resistive memory device includes a memory cell array in which a plurality of memory cells are arranged. Each of the plurality of memory cells includes a variable resistor comprising a first end connected to a bit line, and a second end, a row transistor connected between a row source line and the second end of the variable resistor, the row transistor being selectable by a row word line, and a column transistor connected between a column source line and the second end of the variable resistor, the column transistor being selectable by a column word line. Based on the row transistor being selected, first data is written or second data is read in a row direction of the memory cell array, and based on the column transistor being selected, the first data is written or the second data is read in a column direction of the memory cell array.


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