The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Jul. 24, 2018
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Seok Noh, Chungcheongnam-do, KR;

In-Hyo Han, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G09G 3/3674 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0871 (2013.01); G09G 2310/0218 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01);
Abstract

Disclosed herein are a gate driver including at least two output buffers to drive at least two gate lines and capable of reducing an output deviation of each output buffer, and a flat panel display device including the same. The gate driver includes a plurality of gate-in-panels (GIPs) for sequentially supplying scan signals to a plurality of gate lines. Each GIP includes one carry signal output unit and at least two scan signal output units to drive at least two gate lines, and the carry signal output unit includes a pull-up transistor controlled by a voltage of a first node, a pull-down transistor controlled by a voltage of a second node, and a boosting capacitor formed between gate and source electrodes of the pull-up transistor.


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