The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Apr. 22, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Robert Birke, Kilchberg, CH;

Yiyu Chen, Thalwil, CH;

Navaneeth Rameshan, Adliswil, CH;

Martin Schmatz, Rueschlikon, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0831 (2016.01); G06F 12/0804 (2016.01); G06F 12/0877 (2016.01); G06F 12/0873 (2016.01); G06F 12/0871 (2016.01); G06F 12/0868 (2016.01); G06F 12/0842 (2016.01); G06F 11/34 (2006.01); G06F 9/455 (2018.01); G06F 12/084 (2016.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0831 (2013.01); G06F 9/45533 (2013.01); G06F 11/34 (2013.01); G06F 12/0804 (2013.01); G06F 12/0842 (2013.01); G06F 12/0868 (2013.01); G06F 12/0871 (2013.01); G06F 12/0873 (2013.01); G06F 12/0877 (2013.01); G06F 12/084 (2013.01); G06F 12/0897 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/152 (2013.01); G06F 2212/502 (2013.01);
Abstract

A method for coordinating cache and memory reservation in a computerized system includes identifying at least one running application, recognizing the at least one application as a latency-critical application, monitoring information associated with a current cache access rate and a required memory bandwidth of the at least one application, allocating a cache partition, a size of the cache partition corresponds to the cache access rate and the required memory bandwidth of the at least one application, defining a threshold value including a number of cache misses per time unit, determining a reduction of cache misses per time unit, in response to the reduction of cache misses per time unit being above the threshold value, retaining the cache partition, assigning a priority of scheduling memory request including a medium priority level, and assigning a memory channel to the at least one application to avoid memory channel contention.


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