The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Nov. 12, 2018
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Sumangala Bannur Subraya, Bangalore, IN;

Paulose Kuriakose Arackal, Bangalore, IN;

Sreenivasa Prasad Vellalore, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); H04L 12/931 (2013.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 13/385 (2013.01); G06F 13/404 (2013.01); G06F 13/4022 (2013.01); H04L 49/354 (2013.01); H04L 49/357 (2013.01); G06F 2009/45595 (2013.01); G06F 2213/0058 (2013.01);
Abstract

Example implementations relate to virtual host bus adapter logins. A hypervisor may comprise a processing resource and a memory resource storing non-transitory machine-readable instructions to cause the processing resource to query a computing device to determine port identity information of a plurality of virtual host bus adapters (VHBAs) associated with a physical host bus adapter (HBA) of the computing device and uplink mappings for the plurality of VHBAs, determine a bandwidth allocation of each of the plurality of VHBAs, rank each of the plurality of VHBAs, and cause each of the plurality of VHBAs to login via the determined uplink mappings based on the rank of each of the plurality of VHBAs.


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