The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Aug. 10, 2016
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Edmund Mark Schneider, Austin, TX (US);

Daniel J. Allen, Austin, TX (US);

Saurabh Singh, Cedar Park, TX (US);

Aniruddha Satoskar, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/3234 (2019.01); H03M 1/18 (2006.01); H03M 1/00 (2006.01); G06F 1/26 (2006.01); H03M 1/12 (2006.01); H04R 3/04 (2006.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3234 (2013.01); G06F 1/266 (2013.01); H03M 1/002 (2013.01); H03M 1/12 (2013.01); H03M 1/188 (2013.01); H04R 3/04 (2013.01); G06F 1/3203 (2013.01);
Abstract

A system may include a plurality of processing paths and a controller. The processing paths may include a first processing path configured to generate a first digital signal based on an analog input signal and one or more other processing paths each configured to consume a smaller amount of power than the first processing path, and each configured to generate a respective digital signal based on the analog input signal, wherein one of the other processing paths has a noise floor based on fidelity characteristics of the analog input signal or subsequent processing requirements of a digital output signal generated from at least one of the first digital signal and the respective digital signals. The controller may be configured to select one of the first digital signal and the respective digital signals as the digital output signal of the processing system based on a magnitude of the analog input signal.


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