The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2020
Filed:
Oct. 27, 2016
Nvidia Corporation, Santa Clara, CA (US);
Milind Sonawane, San Jose, CA (US);
Amit Sanghani, San Jose, CA (US);
Jonathon E. Colburn, Ben Lomond, CA (US);
Bala Tarun Nelapatla, Milpitas, CA (US);
Shantanu Sarangi, Saratoga, CA (US);
Rajendra Kumar reddy.S, Bangalore, IN;
Sailendra Chadalavada, Milpitas, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.