The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2020

Filed:

Nov. 28, 2018
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Hidenari Kanehara, Kyoto, JP;

Yasuo Miyake, Osaka, JP;

Sanshiro Shishido, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 3/14 (2006.01); H04N 5/335 (2011.01); H04N 5/3745 (2011.01); H01L 27/146 (2006.01); H04N 5/378 (2011.01); H04N 5/374 (2011.01); H04N 5/376 (2011.01);
U.S. Cl.
CPC ...
H04N 5/3745 (2013.01); H01L 27/14603 (2013.01); H04N 5/376 (2013.01); H04N 5/378 (2013.01); H04N 5/3741 (2013.01); H01L 27/14634 (2013.01);
Abstract

An imaging device having pixels in a row which include: first pixel including a first photoelectric converter and a first transistor having a first control terminal; second pixel including a second photoelectric converter and a second transistor having a second control terminal; third pixel including a third photoelectric converter and a third transistor having a third control terminal; and fourth pixel including a fourth photoelectric converter and a fourth transistor having a fourth control terminal. The device further including input signal line, a signal for controlling the first to fourth transistors input to the signal line; first buffer circuit having a first input terminal coupled to the signal line, and a first output terminal coupled to the first and second control terminals; and second buffer circuit having a second input terminal coupled to the signal line and a second output terminal coupled to the second and third control terminals.


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