The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2020

Filed:

May. 15, 2019
Applicant:

Raydium Semiconductor Corporation, Hsinchu, TW;

Inventors:

Shen-Xiang Lin, Taipei, TW;

Hsuan-Hao Chien, Taipei, TW;

Chih-Jen Hung, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/32 (2007.01); H02M 1/36 (2007.01); G05F 1/46 (2006.01); H02M 3/158 (2006.01);
U.S. Cl.
CPC ...
H02M 1/32 (2013.01); G05F 1/468 (2013.01); H02M 1/36 (2013.01); H02M 3/1584 (2013.01); H02M 2003/1586 (2013.01);
Abstract

A soft-start control circuit includes first to third inverters, first to third comparators, first to fourth resistors, first to fourth D-type flip-flops and a NOR gate. The first comparator outputs a first trigger signal. The second comparator outputs a second trigger signal. The third comparator outputs a third trigger signal. The first D-type flip-flop outputs a first error amplification ready signal. The second D-type flip-flop outputs a second error amplification ready signal. The third D-type flip-flop outputs a high-level output voltage ready signal. The fourth D-type flip-flop outputs a low-level output voltage ready signal. The NOR gate receives an inverted signal of a high-level output voltage enable signal and the third trigger signal and outputs a high-level output voltage control signal to prevent an inrush current of the DC-DC conversion system during a startup process.


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