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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10541328 B1

PDFFull Text
Date of Patent:
Jan. 21, 2020

Filed:

Dec. 19, 2018

Semiconductor device capable of high-voltage operation

Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Cheng-Hua Lin, Hsinchu, TW;

Yan-Liang Ji, Hsinchu, TW;

Chih-Wen Hsiung, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Nicholas J Tobergte

Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 27/06 (2006.01); H01L 49/02 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7817 (2013.01); H01L 27/0629 (2013.01); H01L 28/60 (2013.01); H01L 29/0649 (2013.01); H01L 29/1095 (2013.01); H01L 29/402 (2013.01); H01L 29/42376 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01); H01L 29/7831 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

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