The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2020

Filed:

Jan. 31, 2017
Applicant:

Sumitomo Electric Industries, Ltd., Osaka, JP;

Inventor:

Hirotaka Oomori, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/18 (2006.01); H02M 1/32 (2007.01); H01L 21/48 (2006.01); H01L 23/62 (2006.01); H01L 25/07 (2006.01); H01L 25/16 (2006.01); H02M 7/00 (2006.01); H02M 7/537 (2006.01); H01L 23/36 (2006.01); H01L 23/498 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/4846 (2013.01); H01L 23/62 (2013.01); H01L 25/072 (2013.01); H01L 25/16 (2013.01); H01L 25/18 (2013.01); H02M 1/32 (2013.01); H02M 7/003 (2013.01); H02M 7/537 (2013.01); H01L 23/36 (2013.01); H01L 23/3675 (2013.01); H01L 23/49811 (2013.01); H01L 23/5383 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/4917 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H02M 2001/325 (2013.01);
Abstract

A semiconductor module according to one embodiment includes a circuit substrate and first and second transistors for upper and lower arms of a power conversion circuit. The circuit substrate includes a substrate having first and second insulating parts and a conductive layer disposed therebetween, first and second input interconnection patterns coupled to the first and second input terminals, and an output interconnection pattern coupled to an output terminal. The first and second transistors are electrically coupled to the first and second input terminals through the first and second input interconnection patterns, respectively. The conductive layer has a first area situated opposite the first input interconnection pattern and a second area electrically coupled to the first area. The second area is electrically coupled to the second input interconnection pattern. The conductive layer is insulated from the first input interconnection pattern and the output interconnection pattern by the second insulating part.


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