The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2020
Filed:
May. 02, 2019
Applicant:
SK Siltron Co., Ltd., Gumi-si, Gyeongsangbuk-do, KR;
Inventor:
Jae Hyeong Lee, Gumi-si, KR;
Assignee:
SK SILTRON CO., LTD., Gum-si, Gyeongsangbuk-Do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/30 (2006.01); H01L 21/66 (2006.01); H01L 29/32 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01L 21/324 (2013.01); H01L 22/20 (2013.01); H01L 22/24 (2013.01); H01L 29/32 (2013.01);
Abstract
A wafer defect analysis method according to one embodiment comprises the steps of: thermally treating a wafer at different temperatures; measuring an oxygen precipitate index of the thermally treated wafer; determining a characteristic temperature at which the oxygen precipitate index is maximized; and discriminating a type of defect region of the wafer depending on the determined characteristic temperature.
Lee, Jae. (2020). Wafer and wafer defect analysis method (U.S. Patent No. 10541181). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10541181
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile