The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2020
Filed:
Aug. 31, 2018
Texas Instruments Incorporated, Dallas, TX (US);
Chiraag Juvekar, Cambridge, MA (US);
Joyce Kwong, Dallas, TX (US);
Clive Bittlestone, Allen, TX (US);
Srinath Ramaswamy, Murphy, TX (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
Read-only ('RO') data consisting of a physically unclonable function ('PUF') pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.