The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2020

Filed:

Oct. 17, 2017
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jiha Kim, Beijing, CN;

Seung Woo Han, Beijing, CN;

Guangliang Shang, Beijing, CN;

Xing Yao, Beijing, CN;

Haoliang Zheng, Beijing, CN;

Mingfu Han, Beijing, CN;

Zhichong Wang, Beijing, CN;

Lijun Yuan, Beijing, CN;

Yun Sik Im, Beijing, CN;

Jing Lv, Beijing, CN;

Yinglong Huang, Beijing, CN;

Xue Dong, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G11C 19/28 (2006.01); G09G 3/3266 (2016.01); G09G 3/20 (2006.01); G11C 19/18 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G09G 3/20 (2013.01); G09G 3/3266 (2013.01); G11C 19/184 (2013.01); G11C 19/28 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01);
Abstract

A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.


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