The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2020

Filed:

Dec. 22, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Fausto Artico, Santo Stino di Livenza, IT;

Jose R. Brunheroto, Mohegan Lake, NY (US);

Juan Gonzalez Garcia, Yorktown Heights, NY (US);

Nelson Mimura Gonzalez, Yorktown Heights, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/329 (2019.01); G06T 1/20 (2006.01); G06F 1/324 (2019.01); G06F 11/34 (2006.01); G06F 1/3234 (2019.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 1/324 (2013.01); G06F 1/325 (2013.01); G06F 11/3409 (2013.01); G06F 2201/805 (2013.01); G06N 20/00 (2019.01);
Abstract

Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.


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