The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2020
Filed:
Apr. 19, 2018
Renesas Electronics Corporation, Tokyo, JP;
Hajime Yamashita, Tokyo, JP;
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Abstract
Error notification by a bus master for a speculative access and error notification by a bus slave for a non-speculative access are achieved while a circuit scale of the bus master is suppressed. A bus request includes mode information for selecting that error notification for an access is performed by the bus slave or the bus master. In a case where the mode information indicating that error notification is performed by the bus slave is included in the bus request, when an error for an access in that bus request has occurred, the bus slave performs error notification. In a case where execution of an instruction of a speculative load access has been fixed and error information for the load access has been received from the bus slave, the bus master performs error notification based on the error information.