Processor and instruction code generation device

Abstract

In a processor including an instruction prefetch buffer to prefetch a group of instructions with continuous addresses from a memory, the probability of occurrence of the situation where a bus is occupied by the instruction prefetch more than necessary is reduced. The processor includes an instruction fetch address generator which controls the address and amount of the instruction to be prefetched to the instruction prefetch buffer. The instruction fetch address generator includes a table which stores an instruction prefetch amount of an instruction to make the instruction prefetch buffer perform prefetching in association with a branch destination address of a branch arising in the process execution unit. When a branch arises in the process execution unit, the instruction fetch address generator makes an instruction prefetch buffer prefetch the instruction of the instruction prefetch amount corresponding to the branch destination address concerned including the branch destination address of the arisen branch.