The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2020

Filed:

Jun. 29, 2018
Applicant:

Nichia Corporation, Anan-shi, Tokushima, JP;

Inventors:

Shinichi Daikoku, Tokushima, JP;

Daisuke Sanga, Tokushima, JP;

Assignee:

NICHIA CORPORATION, Anan-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 33/00 (2010.01); H01L 33/60 (2010.01); H01L 33/50 (2010.01); H01L 33/54 (2010.01); H01L 33/62 (2010.01); H01L 33/38 (2010.01); H01L 33/20 (2010.01); H01L 33/22 (2010.01); H01L 33/40 (2010.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 33/0075 (2013.01); H01L 33/0079 (2013.01); H01L 33/20 (2013.01); H01L 33/22 (2013.01); H01L 33/382 (2013.01); H01L 33/507 (2013.01); H01L 33/54 (2013.01); H01L 33/60 (2013.01); H01L 33/62 (2013.01); H01L 33/405 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0033 (2013.01); H01L 2933/0041 (2013.01); H01L 2933/0066 (2013.01);
Abstract

A method of manufacturing a light emitting device includes: providing a semiconductor stack including a first semiconductor layer and a second semiconductor layer; forming light emitting cells by forming grooves in column and row directions; exposing a portion of the first semiconductor layer from the second semiconductor layer in each light emitting cell; forming a first insulation layer having a first hole on the light emitting cells and the grooves; forming a wiring electrode to be in electrical connection with the first semiconductor layer at the first hole in each light emitting cell; forming a second hole in the first insulation layer; forming a second electrode to be in electrical connection with the second semiconductor layer at the second hole; thinning the first semiconductor layer; and exposing the first insulation layer from the first semiconductor layer at the grooves while roughening the surface of the first semiconductor layer.


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