The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2020
Filed:
May. 23, 2018
Samsung Electronics Co., Ltd., Suwon-si, KR;
Hoon Seok Seo, Suwon-si, KR;
Jong Min Baek, Seoul, KR;
Su Hyun Bark, Suwon-si, KR;
Sang Hoon Ahn, Hwaseong-si, KR;
Hyeok Sang Oh, Suwon-si, KR;
Eui Bok Lee, Seoul, KR;
SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.