The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2020

Filed:

Mar. 26, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Eric P. Lewandowski, Morristown, NJ (US);

Jae-Woong Nah, Closter, NJ (US);

Peter J. Sorce, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/027 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H05K 3/06 (2006.01); H05K 3/12 (2006.01); H05K 3/34 (2006.01); H05K 3/40 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/0273 (2013.01); H01L 21/32051 (2013.01); H01L 21/32133 (2013.01); H01L 21/4853 (2013.01); H01L 23/49838 (2013.01); H05K 3/064 (2013.01); H05K 3/12 (2013.01); H05K 3/3457 (2013.01); H01L 23/49866 (2013.01); H01L 23/49894 (2013.01); H01L 2224/11 (2013.01); H05K 3/4007 (2013.01); H05K 2203/04 (2013.01);
Abstract

A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.


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