The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2020
Filed:
Jan. 11, 2018
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Yanghee Lee, Incheon, KR;
Jonghyuk Park, Hwaseong-si, KR;
Choongseob Shin, Uiwang-si, KR;
Hyojin Oh, Seongnam-si, KR;
Boun Yoon, Seoul, KR;
Ilyoung Yoon, Hwaseong-si, KR;
Assignee:
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 27/108 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2006.01); H01L 49/02 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 21/481 (2013.01); H01L 21/76898 (2013.01); H01L 25/0657 (2013.01); H01L 27/10808 (2013.01); H01L 27/10852 (2013.01); H01L 2225/06541 (2013.01);
Abstract
A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.