The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2020

Filed:

Nov. 21, 2017
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Jonathan Curtis Beard, Austin, TX (US);

Roxana Rusitoru, Cambridge, GB;

Curtis Glenn Dunham, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1009 (2016.01); G06F 12/0802 (2016.01); G06F 12/06 (2006.01); G06F 12/0862 (2016.01); G06F 12/1045 (2016.01); G06F 12/1072 (2016.01); G06F 12/1081 (2016.01); G06F 12/109 (2016.01); G06F 12/1036 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 12/0653 (2013.01); G06F 12/0802 (2013.01); G06F 12/0862 (2013.01); G06F 12/109 (2013.01); G06F 12/1063 (2013.01); G06F 12/1072 (2013.01); G06F 12/1081 (2013.01); G06F 12/1036 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/152 (2013.01); G06F 2212/154 (2013.01); G06F 2212/60 (2013.01); G06F 2212/6024 (2013.01); G06F 2212/62 (2013.01); G06F 2212/651 (2013.01); G06F 2212/657 (2013.01);
Abstract

A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.


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