The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2020

Filed:

Sep. 20, 2017
Applicant:

Seagate Technology Llc, Cupertino, CA (US);

Inventors:

Mark Ish, Sandy Springs, GA (US);

Siddhartha Kumar Panda, Bangalore, IN;

Dileep Kumar Sharma, Bangalore, IN;

Durga Prasad Bhattarai, Bangalore, IN;

Assignee:

Seagate Technology LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 3/06 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0607 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Method and apparatus for asynchronous discovery of processing and storage nodes coupled via an expander switch in a fabric. In some embodiments, an initiator device operates as a processing node to transfer data to and from a non-volatile memory (NVM) of a target device at a storage node. One of the initiator or target devices is activated prior to the other device. The second activated device broadcasts a discovery command responsive to the activation of the second activated device and prior to receipt of a request for the discovery command from the first activated device. The first activated device processes the discovery command to establish an I/O communication link between the first activated device and the second activated device. The discovery command may include a non-volatile memory express (NVMe) controller list, and the NVM may be arranged as one or more NVMe namespaces.


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