The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Jan. 24, 2018
Applicant:

Lg Innotek Co., Ltd., Seoul, KR;

Inventors:

Yun Mi Bae, Seoul, KR;

Soon Gyu Kwon, Seoul, KR;

Sang Hwa Kim, Seoul, KR;

Sang Young Lee, Seoul, KR;

Jin Hak Lee, Seoul, KR;

Han Su Lee, Seoul, KR;

Dong Hun Jeong, Seoul, KR;

In Ho Jeong, Seoul, KR;

Dae Young Choi, Seoul, KR;

Jung Ho Hwang, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/24 (2006.01); H05K 3/18 (2006.01); H05K 3/10 (2006.01); H05K 1/09 (2006.01); C25D 3/48 (2006.01); C25D 5/02 (2006.01); C25D 5/48 (2006.01); C25D 7/12 (2006.01); C25D 3/38 (2006.01);
U.S. Cl.
CPC ...
H05K 3/244 (2013.01); H05K 1/09 (2013.01); H05K 1/11 (2013.01); H05K 3/108 (2013.01); H05K 3/181 (2013.01); H05K 3/188 (2013.01); C25D 3/38 (2013.01); C25D 3/48 (2013.01); C25D 5/022 (2013.01); C25D 5/48 (2013.01); C25D 7/123 (2013.01); H05K 2201/0338 (2013.01); H05K 2201/098 (2013.01); H05K 2201/099 (2013.01); H05K 2201/0989 (2013.01); H05K 2203/1184 (2013.01);
Abstract

A printed circuit board includes: an insulating layer; a plating seed layer disposed on the insulating layer; a circuit pattern layer disposed on the plating seed layer and formed of copper (Cu); and a surface treatment layer disposed on the circuit pattern layer and formed of gold (Au), wherein the circuit pattern layer includes a corner portion of an upper portion which has a curvature, and wherein the corner portion of the circuit pattern layer is a boundary surface between the top surface and a side surface of the circuit pattern layer, and the boundary surface has a concavely curved surface.


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