The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Feb. 22, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Bruno Miguel Vaz, Alcabideche, PT;

Brendan Farley, Donabate, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/10 (2006.01); H03M 1/12 (2006.01); H03M 1/46 (2006.01); H03M 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1028 (2013.01); H03M 1/1215 (2013.01); H03M 1/46 (2013.01); H03M 1/00 (2013.01); H03M 1/06 (2013.01); H03M 1/10 (2013.01); H03M 1/12 (2013.01); H03M 1/1245 (2013.01);
Abstract

An analog-to-digital converter (ADC) circuit () and method of operation are disclosed. In some aspects, the ADC circuit () may include a plurality of channels (), a gain calibration circuit (), and a time-skew calibration circuit (). Each of the plurality of channels () may include an ADC (), a switch () configured to provide a differential input signal to the ADC (), a calibration device (), a multiplier (), and a pseudorandom bit sequence (PRBS) circuit () to provide a pseudorandom number (PN) to the switch (), to the calibration device (), and to the multiplier (). In some embodiments, the calibration device () may include first and second offset calibration circuits (-) coupled in parallel between a de-multiplexer (D) and a multiplexer (M) that alternately route signals to the first and second offset calibration circuits (-) based on the pseudorandom number (PN).


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