The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2020
Filed:
Sep. 05, 2018
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Yipeng Wang, Singapore, SG;
Kee Hian Tan, Singapore, SG;
Stanley Y. Chen, Cupertino, CA (US);
Yohan Frans, Palo Alto, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H03B 19/12 (2006.01); H03L 7/197 (2006.01); H03L 7/193 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1976 (2013.01); H03L 7/193 (2013.01);
Abstract
A frequency divider circuit () includes a frequency sub-divider () to provide a frequency divided clock, a delay circuit () configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit () configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.