Receiver-side setup and hold time calibration for source synchronous systems

Abstract

A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.